Reference is made to FIG. 1, which shows a circuit diagram for a conventional boost DC-DC converter circuit 10. A DC input voltage Vin is applied to an input node 12 and the circuit 10 generates a DC output voltage Vout at an output node 14. An inductor 16 is connected between the input node 12 and an intermediate node 18. A first transistor switch 20 (also referred to as a low-side switch) is connected between the intermediate node 18 and ground. The first transistor switch 20 may, for example, comprise an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to ground. A control terminal of the first transistor switch 20 is driven by a pulse width modulated (PWM) drive signal 24. A second transistor switch 26 (also referred to as a high-side switch) is connected between the intermediate node 18 and the output node 14. The second transistor switch 26 may, for example, comprise an n-channel power transistor device having a drain terminal connected to the intermediate node 18 and a source terminal connected to the output node 14. A control terminal of the second transistor switch 20 is driven by a signal 30 which is 180° out of phase from (for example, a logical inversion of) the pulse width modulated (PWM) drive signal 24. A resistive voltage divider 34 is connected between the output node 14 and ground. The divider 34 is formed by the series connection of a first resistor 36 and a second resistor 38. A feedback voltage Vfb is generated at a tap node of the divider 34 between resistors 36 and 38, with the feedback voltage Vfb being a scaled version of the output voltage Vout. An output capacitor 40 is connected between the output node 14 and ground. The PWM drive signals 24 and 30 are generated by a PWM control circuit 44 in response to a comparison of the feedback voltage Vfb with a reference voltage Vref.
In operation, the drive signal 24 is asserted to turn on the low-side transistor 20. This connects the inductor 16 between the input node 12 and ground, and the current through the inductor increases. The drive signal 24 is then deasserted to turn off the low-side transistor 20 and the drive signal 30 is asserted to turn on the high-side transistor 26. The inductor current then discharges to the output capacitor 40 and the output voltage Vout rises. The output voltage Vout is sensed through the resistive voltage divider 34 to generate the feedback voltage Vfb, which is compared to the reference voltage Vref. The difference between Vfb and Vref, referred to as an error voltage, is used by the PWM control circuit 44 to set the length of time that the drive signal 24 is asserted to turn on the low-side transistor 20. One cycle of the PWM control signal for driving transistors 20 and 26 is formed by the on-time (Ton) of the low-side transistor 20 and the subsequent off-time (Toff) of the low-side transistor 20 (with the duty cycle of the PWM control signal being equal to Ton/(Ton+Toff)).
The DC-DC converter should be able to maintain a given performance even in conditions where the magnitude of the input voltage Vin is at a level that is very close to the desired magnitude of the output voltage Vout. Such operation is critical for a boost DC-DC converter; in fact, the closer that Vin gets to Vout, the more the converter struggles to accomplish small duty-cycles for the PWM control signals and performs poorly. In these harsh situations, the required duty-cycle for the PWM control signals should approach zero in order to maintain output regulation. More particularly, for a fixed frequency boost DC-DC converter this means that the on-time (Ton) of the drive signal 24 that is asserted to turn on the low-side transistor 20 should be reduced to zero. Unfortunately, there are problems with this because the on-time Ton is bottom-limited and cannot be reduced to zero. This is due to the fact that propagation delays, power transistor turn-on/off times and dead-times are unavoidable and limit the minimum feasible value for the on-time Ton.
A bottom limited on-time Ton translates to a bottom limited minimum current that accumulates inside the inductor 16 during on-time Ton and transfers to the output during off-time Toff with each cycle of converter operation. Such a limitation leads to an unavoidable natural skip behavior. In fact, when the voltage level of the input voltage Vin is very close to the output voltage Vout, skip mode occurs when the boost DC-DC converter is no longer able to perform with the theoretically required small duty-cycle. In other words, since the converter is not able to reduce its on-time Ton, it accumulates and then transfers on the output 14 a minimum current that is too high and Vout increases. As a result, the converter goes out of regulation. In these situations, it is common for the converter action to be inhibited by skipping one or more switching cycles, in order to regain the ability to maintain a regulated operation. As a result, no charge is delivered to the output when a switching cycle is skipped during skip mode.
Skip mode operation, however, inherently produces an undesirable output ripple that is greater than the ripple which occurs in the normal operating mode (i.e., continuous-conduction-mode (CCM)) for the boost converter. In some applications where boost converters are used, such behavior is not allowed. For example, in AMOLED applications the display-panel positive regulated supply is provided by the boost DC-DC converter and the output ripple on such rail directly translates into display flickering. Because of this, the output ripple must be minimized. For this reason, the DC-DC boost converter must remain in continuous-conduction-mode, and skip mode must be avoided.
A first possible solution to this problem is to instead use a buck-boost topology for the DC-DC converter. This would solve the skip mode related issues and would maintain the converter always in CCM as Vin approaches Vout. However, there is an unacceptable price to pay for using the buck-boost topology in many applications: the circuit topology requires more power transistor devices, is more complex, requires a larger silicon area for a comparable efficiency and experiences a higher current leakage through the power transistor devices.
A second possible solution is to exploit different control schemes. For example, the DC-DC frequency can be changed and reduced in order to achieve smaller duty-cycles (e.g., constant-on-time (COT) control, pulse frequency modulation (PFM) and so on). Such alternative solutions are not always possible due to customer requirements. Indeed, in some applications the customer explicitly requests the use of a fixed-frequency boost DC-DC converter (with a strictly imposed working frequency) and in those cases alternate control schemes are not an option.